Instruction set and Addressing mode

Addressing Modes

Addressing mode are aspect of instruction set architecture. Defines how the instructions identifies the operand.

Immediate Addressing

• operand is present in the instruction
• typically number will be stored in 2's compliment form
• no memory reference other that instruction fetch is needed to get operand
• Limits the size of number with size of address field
• ADD R4, #5
• reg[R4] <--- reg[R4] + 5

Direct Addressing

• Address field contains effective address of the operand
• EA = A
• Single memory reference to get operand and no special calculations involved
• Limited address space
• ADD R4, 3000
• reg[R4] <------ reg[R4] + mem[3000]

Indirect Addressing

• with direct lenght of address field is usually less than word limiting the address range
• address field refers to address of word in the memory which in turn contains the full length address of operand
• two memory reference
• ADD R4, 3000
• reg[R4] <------ reg[R4] + mem[mem[3000]]
• number of words that can be addressed has increased but number of different effective address that may be referenced is still limited

Register Addressing

• address field refers to register rather than main memory
• only a small address field is needed as there are few registers
• no memory reference
• Limited address space
• ADD R4,R3,R2
• reg[R4] <--- reg[R3]+reg[R2]

Register indirect addressing

• accessed using computed address
• ADD R4,(R1)
• reg[R4] <--- reg[R4] + mem[reg[R1]

Displacement Addressing
direct addressing + register indirect addressing
Effective address = A + content of register R

1)relative addressing
the implicitly referenced register is PC that is A is added to PC to get EA
effective address is displacement relative to address of the instruction
exploits concept of locality
A + PC

2)base register addressing
the referenced register contains a memory address and address field contains a displacement(usually unsigned)
A + mem[mem[R]]
exploits locality of reference

3)Indexing
A= main memory address
R=displacement from that address

EA = A + content(R)
A lenght comparibly large than base register addressing

Auto indexing
index register, that is R displacement register, are used in iterative task so need to increment and decrement to address arrays or memory
automatically done part of same instruction cycle

EA = A + content(R)
R = R + 1

Post indexing
indirect addressing +  indexing
EA = content of A + content of R

preindexing EA = contents of (A + content (R))


Problem address stored in PC=X1 Instruction in X1 has addre ss part X2.The operands needed to execute the instruction is stored in memory word with address X2 An indext register contains the value X4 what is relationship between this when addressing mode is
1)direct
X3=X2

2)indirect
X2 should contain address of X3
that is content(X2) =X3
3)PC relative
X3= PC + displacement +1
X3=X1+X2+1
4)indexing
X3=X2 + index
X3=X2+X4

Problem If current instruction is 256028 in decimal and each instruction is 3 byte. offset is -31 find EA PC relative addressing
Solution
EA for pc address = next instruction address + offset(signed number)
next instruction address =  256028+3
EA = 256031 - 31 = 256000

EA for pc address = next instruction address + offset(signed number)

Problem A pC relative mode branch instruction is stored in memory at address 620 The branch is made to location 530 The address field in instruction is 10bit long
What is binary value in instruction
Solution Assuming offset is stored in 2's compliment because it should be signed number it can be negative for branch before and positive for branch after

EA for pc address = next instruction address + offset(signed number)

next instruction address (assuming one instruction per address) = 621
EA we have been given as 530 that is it branches to this address
so 530 - 621 = offset
offset = -91
two's compliment of -91 = 1110100101

Problem how many memory reference when it fetches and executes indirect address mode instruction is
a)computation with single operand
1 for instruction fetch+ 2 memory  reference for indirect address = 3
b)branch instruction
does not need to fetch the operand here only operand reference needed
1 for instruction fetch + 1 operand reference fetch = 2


Problem Instruction length is 16 bit.Operand specifics are 6 bits in length.
number of two operand instruction = K
number of zero operand instruction = L
number of 1 operand instruction = ?
Solution
Total number of bits is 16
total number of possible combinations is 2^16 of which we have to divide them as two operand instruction, one operand instruction and zero
For two operand instruction 12 bits are required for operand

K*2^12 + X*2^6 + L = 2^16Problem A 32bit ISA needs 100 opcodes 3 source operand 2 destination operand. source and destination operands are registers.maximum size of register file?
Solution 100 opcode needs 7 bits
5 operands(source+destination) have available 32-7  =25bits
each register can be addressed with 25/5 bits

 

Problem code to implement A = (B – C)*D in
1) three address instruction
SUB A B C
MPY A A D
2)two address instruction
MOV T1 B
SUB T1 C
MPY T1 D
MOV A T1
3)1 address instruction
LOAD B
SUB C
MPY D
STORE A
4)zero address
PUSH B
PUSH C
SUB
PUSH D
MPY
POP A

all instructions,data values  will be in memory and must be fetched from memory
fetching instruction like SUB A B C
requires 1 byte for opcode 2 byte for each address A B C. 7byte instruction of instruction to fetch

fetching data
each data value 2byte and during execution B and C datavalues will be fetched from the memory and A 2bytes will be written to memeory so total of 7+6 byte of memory traffic

 Unconditional branch
b label ;
assigns value of label to PC

Conditional branch
If condition is true PC is reset to label
If false branch instruction executes no-op
Zero test
beqz x,label   if x==0 then goto label
bnez x       if x!=0 then goto label
bltz less than zero blez if x less than or equal to zero 

Interrupt
Interrupt: depart from normal program sequence, also
called “exception”
Triggered not by instruction in the program itself
Types of interrupts:

– External interrupts: for example, from timing devices, I/O devices
– Internal interrupts: traps (invalid or erroneous use of an
instruction or data), eg. overflow, divide by zero, protection
violation
– Software interrupt: Generate an interrupt explicitly with an
instruction
An interrupt causes the normal program execution to halt and for the interrupt
service routine (ISR) to be executed.

Semiconductor memory
basic element memory cell
cell represent two stable state 1 and 0
capable of being written into, set state
three signals to each cell select(select particular cell) control(specify wether read or write) and read/write

DRAM
individual words of memory are directly accessed through wired -in address logic
RAM volatile(needs continous power, data donot persist on power cut) random access
DRAM stores data as charge on capacitor
capacitors have tendency to discharge so DRAM requires periodic charge refreshing
analogous device
SRAM
digital device uses flipflop logic gate config
DC applied
no refresh needed

comparision Dram and SRAM
both volatile and needs continous power.
DRAM simple small, more dense ,less expensive
DRAM requires refresh opeartion which is costly, favoured for large memory
SRAM generally faster, used as cache

Types of ROM
nonvolatile
can be read only

Problem write assembly code for
for (i=0; i<=100;i++)
 A[i] = B[i] + C;

R1= A[i]
R2=B[i]
R3=C
R4 = i*4

References
http://pages.cs.wisc.edu/~cs354-1/cs354/solutions/adv.hw.sol.html           // floating point and IEEE math
https://www.cis.upenn.edu/~cis501/